Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory, among others.
Flash memory devices are utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption.
Uses for flash memory include memory for personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data, such as a basic input/output system (BIOS), are typically stored in flash memory devices. This information can be used in personal computer systems, among others.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged
A NAND array architecture arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell in a “row” of the array are coupled to a select line. However each memory cell is not directly coupled to a column sense line by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a source line and a column sense line.
Memory cells in a NAND array architecture can be programmed to a desired state. That is, electric charge can be placed on or removed from the floating gate of a memory cell to put the cell into a number of stored states. For example, a single level cell (SLC) can represent two states, e.g., 1 or 0. Flash memory cells can also store more than two states, e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110. Such cells may be referred to as multi state memory cells, multidigit cells, or multilevel cells (MLCs). MLCs can allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one digit, e.g., more than one bit. MLCs can have more than one programmed state, e.g., a cell capable of representing four digits can have sixteen programmed states. For some MLCs, one of the sixteen programmed states can be an erased state. For these MLCs, the lowermost program state is not programmed above the erased state, that is, if the cell is programmed to the lowermost state, it remains in the erased state rather than having a charge applied to the cell during a programming operation. The other fifteen states can be referred to as “non-erased” states.
Flash memory devices can be programmed with various amounts of data at one time. The amount of data programmable at one time can be referred to as a page of data. In some memory devices, one page of data includes data stored on all of the memory cells coupled to a given select line. In other memory devices, data stored on a select line can be divided into more than one page, e.g., into an even page and odd page of data. Various amounts of data can also be erased from a flash device at the same time. The amount of data erasable at one time can be referred to as a block of data. A block of data can include a number of data pages. A memory plane can include a number of data blocks on a given die. Some memory devices have multiple planes per die.
Flash memory devices can store operational information, such as column redundancy, block redundancy, fuse trim, functionality trims, etc. Operational information can be stored in a small mini-array or in the main array of memory cells. Storage in the main array can be beneficial by providing a smaller overall die size compared to a separate mini-array for the same amount of operational information. When operational information is stored in the main array, measures taken to ensure data integrity can be beneficial. One method for storing operational information in the main array includes storing the data in a single select line row with copies of the data in multiple blocks, and planes for devices having more than one plane. Because all blocks on the same plane share common sense lines, defects that prevent operational information from being read in one block can prevent it from being read in any other block on the same plane.